Conventionally, ΔΣ-A/D converters have been known as high-resolution A/D conversion methods (see, for example, Patent Document 1). A ΔΣ-A/D converter includes a ΔΣ-modulator provided at a preceding stage and a digital filter provided at a following stage. The ΔΣ-modulator converts an analog input signal by quantizing the signal with a comparatively coarse number of bits such as one bit or several bits, and outputs the quantized output value (digital signal sequence). In addition, the digital filter removes a quantization error difference from the digital signal sequence, which is the output signal from the ΔΣ-modulator, and performs final digital output.
The ΔΣ-modulator includes a difference signal generator to generate a difference signal between the analog input signal and a feedback signal; an integrator to amplify and to output the difference signal; a quantizer to quantize the output signal from the integrator, by comparing the output signal with a predetermined threshold value; and a D/A converter to apply digital-analog conversion to the output signal from the quantizer to generate the feedback signal. In the ΔΣ-modulator described in Patent Document 1, the integrator includes multiple integrators connected in cascade. Each of the integrators is an active SC integrator using an operational amplifier and a switched capacitor circuit, and includes a sampling capacitor to sample the input signal, and an integration capacitor to execute summing integration with transferred electric charge that has been charged in the sampling capacitor. In each of the integrators, sampling by the sampling capacitor (sampling phase) and integration by the integration capacitor (integration phase) are performed alternately and repeatedly. With such operations, summing integration is performed over differences between the analog input signal and the quantized output at the integrator.
Also, for example, if two stages of integrators are connected in cascade, during an integration phase of the first-stage integrator, the input terminal of the operational amplifier is connected with the first-stage sampling capacitor, whereas the output terminal of the operational amplifier is disconnected from the second-stage sampling capacitor. Also, during a sampling phase of the second-stage integrator, the input terminal of the first-stage operational amplifier is disconnected from the first-stage sampling capacitor, whereas the output terminal of the first-stage operational amplifier is connected with the second-stage sampling capacitor. Configured as such, assuming that the first-stage sampling capacitor and the second-stage sampling capacitor are alternately connected with the operational amplifier of the first-stage integrator, and also assuming that both sampling capacitors are not simultaneously connected with the integrator, then, the drive capability of the operational amplifier is relaxed because the settling time constant of the operational amplifier during an integral operation of the operational amplifier is equalized with the settling time constant in a sampling operation at the next stage.